The present invention relates to a power state management method, and in particular, to a power state management method of north bridge.
Power management is a significant issue in computer design, especially for mobile computing devices. Desired long battery life requires smart and aggressive power management. Units operating at high clock frequencies in a computer system such as central processing units (CPUs), main memories (random access memories, hereafter referred to as RAMs), and chipsets typically consume more power than other units. Those high clock operation units make power management thereof critical.
Advanced Configuration and Power Interface (ACPI) specification 2.0 provides several methods of transitioning computer power states via operating system-directed configuration and power management (OSPM), by which an operating system and a south bridge may transit a computer system through S0, S1, S2, S3, S4, S5 states; and a processor among C0, C1, C2, C3, C4, and other power states.
ACPI defined Processor power states C0˜C3 and system states S0˜S5 are briefly described as follows.
C0 Processor power state: processor executes instructions in this state.
C1 Processor power state: having the lowest latency. A processor is able to maintain the context of system caches.
C2 Processor power state: the state offers improved power savings over the C1 state. A processor is assumed capable of keeping its caches coherent and is able to snoop accessing to main memory.
C3 Processor power state: the state offers improved power savings over the C1 and C2 states. A processor's caches maintain state but the processor isn't required to snoop accessing to main memory. The operating system power management (OSPM) ensures that the caches maintain coherency.
S0 system state: S0 is the system working state. Processors thereof are in the C0, C1, C2, or C3 states. The processor-complex context is maintained and instructions are executed as defined by any of these processor states. Dynamic RAM context is maintained and is read/written by the processors.
S1 sleeping state: S1 state is a low wake latency sleeping state. The processor-complex context is maintained and the processor doesn't execute instructions. Dynamic RAM context is maintained.
S2 sleeping state: S2 state is a low wake latency sleeping state. S2 state conserves more power than S1 state. The processor-complex context isn't maintained and the processor doesn't execute instructions. Dynamic RAM context is maintained. S2 sleeping state is similar to S1 sleeping state except losing the processor-complex context (OS maintains the cache and CPU context).
S3 sleeping state: S3 state is a low wake latency sleeping state. S3 state conserves more power than S2 state. The processor-complex context isn't maintained and the processor does not execute instructions. Dynamic RAM context is maintained.
S4 sleeping state: S4 state is the lowest power, longest wake latency sleeping state supported by ACPI. S4 state conserves more power than S3 state. In the S4 state, the processor does not execute instructions. Both processor-complex context and dynamic RAM context are not maintained.
S5 soft off state: S5 state is similar to the S4 state except that the OSPM does not save any context. The computer system in S5 soft off state requires a complete boot when awakened.
Processor power states affect main memory and chipset activity as well as system states. Power consumption of main memories and chipsets, however, is not well managed with regard to processor power states in conventional computer systems or the ACPI specification.
Typically, a power state machine is built in south bridge; however, conventional north bridge connecting between CPUs and main memories cannot manage power states thereof.